DDECS 2015: ELSYS EE Presents New Direct Test Methodology
DDECS 2015 took place in Belgrade from 22nd until 24th April with more than 90 participants and 60 presented papers. ELSYS Eastern Europe was one of the participants as well as sponsor or this event.
The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of electronic circuits and systems. The DDECS Symposium series has been organized by the following European countries: Czech Republic, Poland, Slovakia, Hungary, Austria, Germany and Estonia.
ELSYS EE paper “Direct test methodology for HDL verification” was presented on this conference. It covers one approach to direct test verification methodology in modern HDL designs with emphasis on some aspects of its current implementation in ELSYS EE. Methodology describes modular flow for requirement driven verification, easy to integrate and reuse both in terms of testbench components and test vectors. As such, it represents a natural evolution of classical HDL testbenches and provides viable alternative to specialized verification procedures.