TWO IN ONE

Thesis or practice – why not both?

Our offer is simple and fair: your graduation thesis and a chance to work on a real commercial project, both done at the same time! The offer includes a scholarship with no contract obligation and no strings attached. This unique chance to work with a world-class semiconductor company based in Serbia comes with full backing of the professors. At Elsys Eastern Europe we can give you guidance through a mentorship program, lab practice, consultations, and a chance to work on a real, commercial project. It’s time to put the theory into practice at a place where your ideas and smarts matter.

This two-in-one offer was carefully made for outstanding final year students of bachelor degree or master students of following departments:

School of Electrical engineering, University of Belgrade

Electronics or Computer Science and Information Theory

 

Faculty of Technical Sciences, University of Novi Sad

E1 – Embedded systems and algorithms, Microelectronics or Applied electronics
E2 – Computing and Control Engineering

Benefits

  • This is your chance to work on an actual project in Digital, Analog and mixed signal IC
  • You will receive a dedicated mentor
  • Worktime is 16 to 24 hours of practice per week in our office, with regards to your university schedule
  • You will be trained by some the best engineers in the region
  • Your work can be the subject of your graduation thesis, master or seminar paper
  • Monthly stipend of 15.000 RSD
  • No lock-in contract obligation

 

 

Conditions

This offer is open to final year students or bachelor degree or master student of School of Electrical engineering or Faculty of Technical Sciences that don’t already receive a scholarship from other companies

 

 

How do I apply

  • CV, written in English
  • Motivational letter
  • Proof of completed exams
  • Optional: A proposal of a subject you would like to work on
  • Application deadline: November 10th

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.