Open Position

Senior Digital Design Engineer

Key Responsibilities / Duties:

  • Handling with complete frontend digital design flow
  • Discussing specifications with our system engineers and translating these into design requirements taking part in micro-architecture
  • Design, IP integration and other tasks as part of the chip development processes

Qualification Requirements:

  • More than 5 years of relevant experience
  • Experience with complete frontend digital design flow – RTL Design, synthesis, formal checks (lint, cdc, …)
  • Experience in micro-architecture and design of complex blocks
  • Strong background in digital electronics, ASIC/FPGA
  • Good Knowledge of processor architecture and Systems On Chip
  • Good understanding of VHDL/Verilog RTL digital design, synchronization and timing
  • Project management skills with a proven record of successful digital design projects is a plus
  • Team leadership skills is plus
  • Script knowledge (TCL, Perl, etc.) is advantage
  • Fluent in English
  • Highly motivated, well organized and team player

Benefits:

  • Integration program in a professional, young & dynamic team
  • Professional development opportunities
  • Competitive salaries & benefits
  • Compensation package includes also additional health insurance, sport & social activities
  • International work environment

You can find out more about our benefits here.




Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.

Ivana Maričić
HR Manager


Apply for:
Senior Digital Design Engineer


GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.