information-technology

Rapid technological advances in the last 30 years have created increasingly complex digital systems. Good architecture development with review of reusability became one of the key factors for a good digital design. Learn more

Design Verification is one of the most important aspects of the IC development process, consuming 60 – 80% of the total IC development resources and time. EEE offers a wide range of solutions in pre-silicon design verification that will allow fast and reliable product development for our customers. Learn more

Over 7 years of experience in mixed-signal domain allows us to successfully cope with any challenge that modern verification methodologies have to offer. Learn more

IC Layout team provides full custom IC physical design service from design requirements and netlist through layout floor-planning, time, resources and area estimation, mixed-signal IP integration and physical verification to mask data generation, tapeout and packaging support. Learn more

HW System Design team has an extensive experience which enables us to seamlessly integrate into customer HW System design and verification teams or to independently manage a complete HW Design project. Highly specialized in HW system design and HW verification & validation. Learn more.

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.