Open Positions

Design Verification

You will be part of digital IP/SoC design verification team, constituted of verification engineers with different level of experience, from digital verification experts to digital verification juniors. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools, and flows.

UVM0%

SoC0%

C/C++0%

Verilog0%

Design Verification Engineer

You will be part of digital IP/SoC design verification team, constituted of verification engineers with different level of experience, from digital verification experts to digital verification juniors. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools, and flows.

C/C++0%

Team leadership skills0%

UVM0%

SoC0%

MS Verification Engineer

You will be a part of an analog and mixed-signal verification and modeling team, constituted of engineers with a different level of experience, from experts to juniors. Involvement in analog IP models development, model calibration (model vs schematic) and close interaction with other IC implementation teams to achieve IC implementation milestones. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools, and flows. Selected candidates will receive full support from our experienced engineers.

Analog electronics0%

Digital electronics0%

Verilog / Verilog-AMS0%

CMOS and bipolar technology0%

Digital Design Engineer

You will be a part of a digital design team with the possibility for leadership, constituted of digital design engineers with different levels of experience, from experts to juniors. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools, and flows.

VHDL/Verilog0%

ASIC/FPGA0%

Processor architecture and SoC0%

C/C++0%

Senior Digital Design

You will be a part of a digital design team with the possibility for leadership, constituted of digital design engineers with different levels of experience, from experts to juniors. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools, and flows.

VHDL/Verilog0%

ASIC/FPGA0%

RTL Design0%

Perl0%

IC Layout Engineer

For our offices in Belgrade and Novi Sad, Serbia, we are looking for proactive and motivated Analog Custom IC Layout Engineers to join our dynamic team. You will be a part of analog layout team, constituted of engineers with different level of experience, from analog layout experts to juniors. Your daily work will be challenging and you will have the opportunity to cooperate with industry experts on the state-of-the-art processes, tools, and flows.

Analog electronics0%

Analog IC design/layout0%

CMOS and bipolar technology0%

CAD tools 0%

On the other hand, if a suitable position in relation to your level of expertise is not on the list but you still feel you belong with Elsys, feel free to send us your curriculum vitae and a cover letter.

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.