ELSYS Eastern Europe provides high quality IC design and verification service, worldwide, ranging from ASIC to the most complex SoC design. Some of the biggest companies in the world entrusted us with their most difficult projects.

It is a sustained effort not to let our clients down. For two decades now we aim to be that one thing they don’t really have to worry about. We are looking forward to be a part of the solution for your company as well. We are a stable supplier, resilient to fluctuations of IFX external needs, with strong quality control and years of experience. As Ernest Hemingway once said: “The best way to find out if you can trust somebody – is to trust them.”

Partnerships & awards

Rapid technological advances in the last 30 years have created increasingly complex digital systems. Good architecture development with review of reusability became one of the key factors for a good digital design. Read more

Design Verification is one of the most important aspects of the IC development process, consuming 60 – 80% of the total IC development resources and time. EEE offers a wide range of solutions in pre-silicon design verification that will allow fast and reliable product development for our customers. Read more

AMS verification focuses on verification of the analog/mixed-signal part of the chip, ensuring that every analog module, their mutual connections as well as connections to the digital core are working and verified properly. There are a couple of approaches to the mixed-signal verification, some focused on digital, some on analog side, but they all ensure that the verification job is well executed and finished successfully. Read more

IC Layout team provides full custom IC physical design service from design requirements and netlist through layout floor-planning, time, resources and area estimation, mixed-signal IP integration and physical verification to mask data generation, tapeout and packaging support. Read more

Industries we support

Automotive

5G

IoT

Medical

Multimedia

Security

Transportation

Wireless

YEAH, WE’RE FROM EASTERN EUROPE

And you know what that means – it means we make things happen!

Honestly, we are as smart as everybody else, but as your future business partners we are in a favorable position and time zone, able to connect and simultaneously cater to US, Europe, Middle East, India and Japan. With an internal training center and strong talent sourcing we bring the brightest problem-solving, bug-catching minds to tackle your projects. Or we can assemble a dedicated team to provide you with an ongoing support.

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.