Design Verification Engineer For The New Generation Of FPGA Chip
Your responsibilities include:
- verification methodology establishment
- development of verification environment
- developing test and functional coverage plans based on device specifications
- analyzing and debugging simulation failures, as well as analyzing functional coverage results
- verification progress tracking and close interaction with other teams in order to achieve product implementation milestones.
Qualification and Key requirements:
- Strong background in digital electronics, ASIC/FPGA
- Good Knowledge of processor architecture and Systems On Chip
- UVM – advantage
- Knowledge of scripting tolls and languages – advantage
- Formal verification – advantage
- Knowledge of DDR, PCIe or HMB (High Bandwidth Memory) – advantage
- Highly motivated, well organized and team player
- Good knowledge of English language
Benefits:
- UVM & Project Ramp-up training will be provided by ELSYS
- Integration program in a professional, young & dynamic team
- Professional development opportunities
- Competitive salaries & benefits
- Compensation package includes also additional health insurance, sport & social activities
- International work environment
You can find out more about our benefits here.
