Pass the Exam.
Win the competition.
All with one project.
Join our TECH+FTN challenge and do what you do best, coding and programming.

In collaboration with the Faculty of Technical Sciences in Novi Sad, we’ve formed a competition that offers their talented 4th year students from Microcomputer Electronics – Embedded Systems and Algorithms course the opportunity to measure their capabilities and discover their potential while overcoming coding challenges and leveling up their skills for programming roles.

Can you bring the project to
its completion in limited time?​

Design of complex digital systems

Real-time microcomputer systems

Design of electronic systems at the system level

Functional hardware verification

Besides for the purposes of the competition, part of the implementation of this project,
team members can use as their graduation thesis.
Step up your coding game!
In order to apply you must assemble a team of maximum 4 of fellow students, or you can apply solo.

Besides being a student of Microcomputer Electronics – Embedded Systems and Algorithms cathedra at Faculty of Technical Sciences, Novi Sad, we’re looking for a passionate team that is willing to push the boundaries and enter the world of electronics with a great solution to our challenge.

application specs

  • Team Name or your name if solo
  • Bios of all team members (age, year of study, department of electronics)
  • For additional information contact us at
    techplus@elsys-eastern.com
  • Application deadline is: 08.04. before 23:59

what now?

Unleash your inner programming guru and apply for our competition.

team application
solo application

prizes

We’ve prepared amazing prizes for winning teams of our TECH+FTN competition.
1st place: 3000€
2nd place: 1500€  

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.