Apply before April 2025!
Make your first step toward a successful career
All candidates will be notified about their application status in a timely manner. Good luck with the interviews!

Junior Business Manager Internship

ELSYS Eastern Europe is looking for a Junior Business Manager Intern to join our team and gain valuable hands-on experience in the business side of engineering services. As part of our dynamic team, you’ll have the opportunity to learn directly from experienced professionals while contributing to real projects in the field. Your duties will include, but not be limited to:

Internship Timeline

6 weeks
(business management fundamentals, organizational behavior)
6 weeks
(leadership, team dynamics, financial management, operations, human resources, project management )
1 week
(Lectures + Lab practice)
Project oriented training until the end of the program

Employee Benefits:

OFFICE BASED ROLE

PROFESSIONAL,
YOUNG & DYNAMIC TEAM​

PROFESSIONAL DEVELOPMENT
OPPORTUNITIES​

COMPETITIVE SALARIES
& BENEFITS​

ADDITIONAL HEALTH INSURANCE,
SPORT & SOCIAL ACTIVITIES​​

INTERNATIONAL WORK ENVIRONMENT &
TRAVELING OPPORTUNITIES​

Required Skills and Qualifications:

Final year student or fresh graduate with B.Sc. or M.Sc. degree in electrical engineering

Motivated, proactive, hard working

Good knowledge of English language

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Apply before April 2025!
Make your first step toward a successful career

All candidates will be notified about their application status in a timely manner.

Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.

Ivana Maričić
HR Manager

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.