Senior Design Verification Engineer
Key Responsibilities / Duties:
- Lead the development of verification environments and integrate verification IPs.
- Design and execute advanced verification strategies, ensuring compliance with device specifications.
- Debug simulation failures and analyzing coverage metrics for optimal test efficiency.
- Manage a team of verification engineers, providing mentorship and technical guidance.
- Track verification progress and engage closely with clients and management.
- Oversee project planning, execution, and risk mitigation to ensure successful implementation.
Qualification & Requirements:
- 5+ years of experience in digital verification, with expertise in UVM/SystemVerilog or Specman/e.
- Strong background in digital electronics, ASIC/FPGA design.
- Proficiency in system architecture including processor architecture.
- Experience in debugging Gate-Level Simulations (GLS) and timing closure.
- Solid understanding of C/C++ and familiarity with scripting tools (Python, Perl, Tcl).
- Proven team leadership and project management skills.
- Willingness to share knowledge and mentor junior engineers.
- Excellent English communication skills.
Benefits:
- Leadership role in a high-performance verification team.
- Competitive salary with benefits, including health insurance and social activities.
- Professional growth opportunities in an international work environment.
- Direct engagement with clients and exposure to cutting-edge verification methodologies.
You can find out more about our benefits here.