If you are a student, HW Design domain is an ideal place to start your ASIC/FPGA chips development run. You can build up your basic knowledge on digital design, VLSI design and microprocessor systems. Our training program will provide you with core education you need to take on a commercial project with highly-experienced engineers as your tutors. Read more about Digital design here.
For someone at the beginning of his career, this is the right field to start as you will acquire a broad knowledge base required to work in SoC verification. Being ready to learn, travel and integrate in a team of likeminded professionals is a must in such a demanding field. Luckily, at Elsys EE we provide full support for your development on this journey. Read more about Verification of digital design here.
This is the field where you can put your university-learned knowledge from analog electronics to practical use. AMS is an integral part of all the verification in mixed-signal chips, and it is one of the most sought-after fields today, as over 90% of all chips in production today are mixed-signal chips. You will collaborate directly with highly-experienced analog designers and enjoy the work in the field that is still in development. Read more about Mixed signal verification here.
Despite the advancements in digital technology, large number of electronic blocs will still remain in the analogue domain as well as the need for their physical design using the Custom IC Layout methodology. Young engineers will find that Elsys EE provides the right support and supervision from highly-experienced colleagues as they work on real projects within our company. Read more about IC layout here.
|1||Clock domain crossing – issues and how to overcome them||DD|
|2||Scheduling techniques and their implementation for queue servicing||DD|
|3||Functional safety approaches implementation in digital design||DD|
|4||Temperature sensor IP – Analysis, modeling and verification||AMS|
|5||Bandgap reference IP – Analysis, modeling and verification||AMS|
|6||Voltage regulator IP – Analysis, modeling and verification||AMS|
|7||Internal oscillator IP – Analysis, modeling and verification||AMS|
|8||Power-on Reset IP – Analysis, modeling and verification||AMS|
|9||IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDP||DV|
|10||IP verification – MAC merge sublayer IP – MMSL – MAC Rx||DV|
|11||IP verification – MAC merge sublayer IP – MMSL – MAC Tx||DV|
|12||SoC integration – 3PIAS Projekat||DD+DV|
|13||SoC integration – ARM – Cortex M0 platform Integration using ARM SDK||DD+DV|
|14||SoC integration – ARM – Cortex M3 platform Integration using ARM SDK||DD+DV|
|15||SoC Verification – interdisciplinary themes – SW coverage collection and analysis||DV|
|16||SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)||DV|
|17||VIP Development – PCI Express||DV|
|18||VIP Development – DDR||DV|
|19||VIP Development – Ethernet||DV|
|20||VIP Development – USB||DV|
|21||VIP Development – CSI||DV|
|22||VIP Development – DSI||DV|
|23||VIP Development – UNIPRO||DV|
|24||VIP Development – I3C||DV|
|25||VIP Development – SLIMbus||DV|
|26||VIP Development – HDMI||DV|