Apply before June 7th 2024!
Make your first step toward a successful career
Make your first step toward a successful career
All candidates will be notified about their application status in a timely manner, while the start is planned for 15th July. Good luck with the interviews!
You will be a part of analog layout team, constituted of engineers with different level of experience, from analog layout experts to juniors. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools and flows.
- Interns will be engaged in analog layout design including:
- Full custom analog IC layout design methodologies
- Using Cadence tools for layout design
- Layout design of several common analog circuits
- Using Cadence tools for layout design verification (DRC/LVS)
- Intern will receive full training and support from our experienced engineers.
- Duration of internship is 3 months and will begin after exams or differently defined with candidate
- Full time internship 40h a week or differently defined with candidate
- Internship project can be subject of a bachelor/master thesis or seminar paper
- Interns will receive monthly compensation
- Company will provide accommodation if interns are outside of Belgrade or Novi Sad
Internship Timeline
5 weeks
(Lectures + Lab practice)
(Lectures + Lab practice)
Analog IC layout methodology and flow basics
CAD tools basics
Introduction to 55nm CMOS
process technology
Standard analog design topologies layout training
Introduction to Linux environment
CAD tools basics
Introduction to 55nm CMOS
process technology
Standard analog design topologies layout training
Introduction to Linux environment
4 weeks
(Lectures + Lab practice)
(Lectures + Lab practice)
Introduction to more advanced IC layout topics
Introduction to more complex circuits and complex hierarchy and requirements
Working on layout and physical verification of 2-3 complex modules
Introduction to more complex circuits and complex hierarchy and requirements
Working on layout and physical verification of 2-3 complex modules
5 weeks
(Lectures + Lab practice)
(Lectures + Lab practice)
Analog IC layout methodology
and flow basics
CAD tools basics
Introduction to 55nm CMOS
process technology
Standard analog design topologies layout training
Introduction to Linux environment
and flow basics
CAD tools basics
Introduction to 55nm CMOS
process technology
Standard analog design topologies layout training
Introduction to Linux environment
4 weeks
(Lectures + Lab practice)
(Lectures + Lab practice)
Introduction to more advanced IC layout topics
Introduction to more complex circuits and complex hierarchy and requirements
Working on layout and physical verification of 2-3 complex modules
Introduction to more complex circuits and complex hierarchy and requirements
Working on layout and physical verification of 2-3 complex modules
Employee Benefits:
FULLY REMOTE
PROFESSIONAL,
YOUNG & DYNAMIC TEAM
PROFESSIONAL DEVELOPMENT
OPPORTUNITIES
COMPETITIVE SALARIES
& BENEFITS
ADDITIONAL HEALTH INSURANCE,
SPORT & SOCIAL ACTIVITIES
INTERNATIONAL WORK ENVIRONMENT &
TRAVELING OPPORTUNITIES
Required Skills and Qualifications:
Motivated, proactive, hard working
Relevant courses/knowledge: basics of analog electronics, VLSI basics
Familiar with basic analog IC design/layout, CMOS technology and IC manufacturing concepts, Cadence tools knowledge is a plus
Good knowledge of English language
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Apply before 31st December 2024!
Make your first step toward a successful career
All candidates will be notified about their application status in a timely manner,
while the start is planned for 3rd March 2025. Good luck with the interviews!
while the start is planned for 3rd March 2025. Good luck with the interviews!
Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.
Ivana Maričić
HR Manager