You will be a part of analog layout team, constituted of engineers with different level of experience, from analog layout experts to juniors. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools and flows.
Interns will be engaged in analog layout design including:
Full custom analog IC layout design methodologies
Using Cadence tools for layout design
Layout design of several common analog circuits
Using Cadence tools for layout design verification (DRC/LVS)
Intern will receive full training and support from our experienced engineers.
Duration of internship is 4 months and will begin in February after exams or differently defined with candidate
Full time internship 40h a week or differently defined with candidate
Internship project can be subject of a bachelor/master thesis or seminar paper
Interns will receive monthly compensation
Company will provide accommodation if interns are outside of Belgrade
Final year student or fresh graduate with B.Sc. or M.Sc. degree in electrical engineering
Motivated, proactive, hard working
Relevant courses/knowledge: basics of analog electronics, VLSI basics
Familiar with basic analog IC design/layout,CMOS technology and IC manufacturing concepts,Cadence tools knowledge is a plus
Good knowledge of English language is a plus
Integration Program in a Professional, Young & Dynamic Team
Professional Development Opportunities
Competitive Salaries & Benefits
Compensation package includes also Additional Health Insurance, Sport & Social activities
International Work Environment & Traveling Opportunities
Deadline for application: 12th January. Interviews are planned for January. The final list of selected candidates will be announced by 27th January.