Submit your application before 14th June.
The final list of selected candidates will be announced by 29th June.
Internship is planned to start by middle of July, however, due to the situation exact date will be announced in a timely manner.

Analog Mixed-Signal Design and Verification Engineer

You will be a part of an analog design and modeling team, constituted of engineers with a different level of experience, from experts to juniors. Involvement in analog IP models development, model calibration (model vs schematic) and close interaction with other IC implementation teams in order to achieve IC implementation milestones. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools, and flows. Selected candidates will receive full training and support from our experienced engineers. The project can be a subject of a bachelor/master thesis or seminar paper.

  • Selected candidates will be engaged in:
  • Development of Verilog A/AMS models of AMS IP
  • Analog and mixed-signal circuits analysis
  • Development of AMS design verification environment
  • Using Cadence toolchain for AMS verification
  • Intern will receive full training and support from our experienced engineers.
  • Duration of internship is 4 months and will begin in July after exams or differently defined with candidate
  • Full time internship 40h a week or differently defined with candidate
  • Internship project can be subject of a bachelor/master thesis or seminar paper
  • Interns will receive monthly compensation
  • Company will provide accommodation if interns are outside of Belgrade or Novi Sad

Internship Timeline

1 week
(lectures + project)
Digital design
3-4 weeks
(lectures + Lab practice)
System Verilog and UVM
1 week
UVC creation of a given module
≈10 weeks
(2 lectures + Lab practice + Final model)
Analog modeling Verilog – AMS
2 weeks
Model integration into UVM environment
1 week
(lectures + project)
Digital design
3-4 weeks
(lectures + Lab practice)
System Verilog and UVM
1 week
UVC creation of a given module
≈10 weeks
(2 lectures + Lab practice + Final model)
Analog modeling Verilog – AMS
2 weeks
Model integration into UVM environment

Employee Benefits:

Professional,
Young & Dynamic Team

Professional Development
Opportunities

Competitive Salaries
& Benefits

Compensation package

Additional Health Insurance,
Sport & Social activities​

International Work Environment & Traveling Opportunities

Required Skills and Qualifications:

Final year student or fresh graduate with B.Sc. or M.Sc. degree in electrical engineering

Motivated, proactive, hard working

Relevant courses/knowledge: basics of analog electronics, VLSI basics

Skills: Familiar with basic analog circuitry, CMOS, and bipolar technology, VHDL or Verilog HDL language, Cadence tools knowledge is a plus

Good knowledge of English language

The button you are searching for
is right here

Submit your application before 14th June.

The final list of selected candidates will be
announced by 29th June.

Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.

Ivana Maričić
HR Manager

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.