Apply before June 7th 2024!
Make your first step toward a successful career
Make your first step toward a successful career
All candidates will be notified about their application status in a timely manner, while the start is planned for 15th July. Good luck with the interviews!
You will be a part of a digital/mixed-signal design verification team, constituted of verification engineers with different level of experience, from verification experts to verification juniors. In order to achieve IC implementation milestones you will be involved in verification methodology establishment, verification plan creation, development of verification environment and close interaction with other IC implementation teams. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools and flows.
- Selected candidates will be engaged in development of a digital/mixed-signal verification environment including:
- architecture definition
- verification environment implementation in SystemVerilog
- verification planning
- full verification in accordance with UVM methodology (SystemVerilog)
- Intern will receive full training and support from our experienced engineers.
- Duration of internship is 3 months and will begin after exams or differently defined with candidate
- Full time internship 40h a week or differently defined with candidate
- Internship project can be subject of a bachelor/master thesis or seminar paper
- Interns will receive monthly compensation
- Company will provide accommodation if interns are outside of Belgrade or Novi Sad
Internship Timeline
1 week
(Lectures + Lab practice)
(Lectures + Lab practice)
Digital design
3 weeks
(Lectures + Lab practice)
(Lectures + Lab practice)
System Verilog and UVM
Project oriented training
until the end of the program
until the end of the program
Project oriented training
until the end of the program
until the end of the program
1 week
(Lectures + Lab practice)
(Lectures + Lab practice)
Digital design
3 weeks
(Lectures + Lab practice)
(Lectures + Lab practice)
System Verilog and UVM
Project oriented training until the end of the program
Employee Benefits:
FULLY REMOTE
PROFESSIONAL,
YOUNG & DYNAMIC TEAM
PROFESSIONAL DEVELOPMENT
OPPORTUNITIES
COMPETITIVE SALARIES
& BENEFITS
ADDITIONAL HEALTH INSURANCE,
SPORT & SOCIAL ACTIVITIES
INTERNATIONAL WORK ENVIRONMENT &
TRAVELING OPPORTUNITIES
Required Skills and Qualifications:
Final year student or fresh graduate with B.Sc. or M.Sc. degree in electrical engineering
Motivated, proactive, hard working
Relevant courses/knowledge: basics of digital electronics, programming,
FPGA basics, microcontroller architecture
Good knowledge of English language
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Apply before 31st December 2024!
Make your first step toward a successful career
All candidates will be notified about their application status in a timely manner,
while the start is planned for 3rd March 2025. Good luck with the interviews!
while the start is planned for 3rd March 2025. Good luck with the interviews!
Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.
Ivana Maričić
HR Manager