Submit your application before 14th June.
The final list of selected candidates will be announced by 29th June.
Internship is planned to start by middle of July, however, due to the situation exact date will be announced in a timely manner.

Digital Design Verification Engineer

You will be a part of a digital/mixed-signal design verification team, constituted of verification engineers with different level of experience, from verification experts to verification juniors. In order to achieve IC implementation milestones you will be involved in verification methodology establishment, verification plan creation, development of verification environment and close interaction with other IC implementation teams. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools and flows.

  • Selected candidates will be engaged in development of a digital/mixed-signal verification environment including:
  • architecture definition
  • verification environment implementation in SystemVerilog
  • verification planning
  • full verification in accordance with UVM methodology (SystemVerilog)
  • Intern will receive full training and support from our experienced engineers.
  • Duration of internship is 3 months and will begin in July after exams or differently defined with candidate
  • Full time internship 40h a week or differently defined with candidate
  • Internship project can be subject of a bachelor/master thesis or seminar paper
  • Interns will receive monthly compensation
  • Company will provide accommodation if interns are outside of Belgrade or Novi Sad

Internship Timeline

1 week
(Lectures + Lab practice)
Digital design
3 weeks
(Lectures + Lab practice)
System Verilog and UVM
Project oriented training
until the end of the program
1 week
(Lectures + Lab practice)
Digital design
3 weeks
(Lectures + Lab practice)
System Verilog and UVM
Project oriented training until the end of the program

Employee Benefits:

Professional,
Young & Dynamic Team

Professional Development
Opportunities

Competitive Salaries
& Benefits

Compensation package

Additional Health Insurance, Sport & Social activities

International Work Environment & Traveling Opportunities

Required Skills and Qualifications:

  • Final year student or fresh graduate with B.Sc. or M.Sc. degree in electrical engineering
  • Motivated, proactive, hard working
  • Relevant courses/knowledge: basics of digital electronics, programming, FPGA basics, microcontroller architecture
  • Skills: VHDL or Verilog, C programming language, object-oriented programming is a plus
  • Good knowledge of English language

The button you are searching for
is right here

Submit your application before 14th June.

The final list of selected candidates will be
announced by 29th June.

Growth empowered by passion and expertise. Employee satisfaction and loyalty are achievable only in environments where mutual understanding, respect, and trust exist. The mission of the HR department is to secure and further nurture these values.

Ivana Maričić
HR Manager

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.