You will be a part of a digital/mixed-signal design verification team, constituted of verification engineers with different level of experience, from verification experts to verification juniors. In order to achieve IC implementation milestones you will be involved in verification methodology establishment, verification plan creation, development of verification environment and close interaction with other IC implementation teams. Your work on these activities will be challenging and you will have the opportunity to work with industry experts on the state-of-the-art processes, tools and flows.
Selected candidates will be engaged in development of a digital/mixed-signal verification environment including:
verification environment implementation in SystemVerilog
full verification in accordance with UVM methodology (SystemVerilog)
Intern will receive full training and support from our experienced engineers.
Duration of internship is 3 months and will begin in February after exams or differently defined with candidate
Full time internship 40h a week or differently defined with candidate
Internship project can be subject of a bachelor/master thesis or seminar paper
Interns will receive monthly compensation
Company will provide accommodation if interns are outside of Belgrade
Final year student or fresh graduate with B.Sc. or M.Sc. degree in electrical engineering
Motivated, proactive, hard working
Relevant courses/knowledge: basics of digital electronics, programming, FPGA basics, microcontroller architecture
Skills: VHDL or Verilog, C programming language, object-oriented programming is a plus
Good knowledge of English language is a plus
Integration Program in a Professional, Young & Dynamic Team
Professional Development Opportunities
Competitive Salaries & Benefits
Compensation package includes also Additional Health Insurance, Sport & Social activities
International Work Environment & Traveling Opportunities
Deadline for application: 12th January. Interviews are planned for January. The final list of selected candidates will be announced by 27th January.