My Engineering Story: Đorđe, SoC Design Verification Engineer

The greatest beauty of the engineering profession lies in the fusion of the aesthetic and the practical on one hand, the beauty of creating something that endures beyond the engineer, and on the other hand, the benefit that others derive from it.

The love for engineering was born while I was still in high school, when it was already becoming clear which professional path I would take. At the urging of my sister (who is also an engineer), I decided on electrical engineering. Mathematics and physics were my two favorite subjects in school, and I saw their concrete application in engineering.

To me, being an engineer means being someone who works in a specific field of industry and contributes to its development as part of a team. The greatest beauty of the engineering profession lies in the fusion of the aesthetic and the practical – on one hand, the beauty of creating something that endures beyond the engineer, and on the other hand, the benefit that others derive from it. As an engineer in the field of chip verification, I am responsible for ensuring that chips used in various industrial domains work flawlessly, which requires me to think systematically and always stay “one step ahead.”

My future plans involve further development in the field of hardware and its verification, as well as in the field of software, as they are inseparable from each other.

If you’ve found Đorđe’s story interesting, check out our Digital Design Verification Engineer program.

WHERE PASSION LEADS TO EXCELLENCE

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GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.