Please submit your application until 12th of May, 2020

WINNING THE FUTURE

The decision to join a big engineering company in semiconductor industry isn’t an easy one so why not take a tour first? You’ll learn about different areas of expertise, semiconductor industry trends and have the opportunity to catch a glimpse of corporate culture as well as working standards required to work with top-notch semiconductor players.

LEARN & GRADUATE

Before you start earning & learning like a professional, you need to decide what field of expertise you want to focus on and probably finish your master thesis. During the Open Day, our senior engineers will share valuable advice on what your first steps should be and how to finish your master thesis during your internship at Elsys Eastern Europe.

CHOICE YOUR EXPERTISE

Learned the theory for years and now when you have to pick the right expertise and the right company, you might require some additional information. Our talented engineers will give you an in-depth view at some of the most promising aspects in the future of hardware engineering. You will also get a chance to see what’s it really like working with us as our junior engineers describe profile of some of the most interesting projects they are working on.

This year, in line with all the health precautions, you can join us in a virtual tour of the company and join many talented engineers as they describe what the future holds for you. Prepare your questions!

Access details will be sent upon registration

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.