Open Day Application


    By completion of this application, I give my consent to Elsys Eastern Europe, Omladinskih brigada 90e, building 2300, 11070 Belgrade, PIB 103329586, to use my personal data to contact me in respect to the event updates and relevant mater.

    GRADUATION THESIS LIST

    #TopicDomain
    1Clock domain crossing – issues and how to overcome themDD
    2Scheduling techniques and their implementation for queue servicingDD
    3Functional safety approaches implementation  in digital designDD
    4Temperature sensor IP – Analysis, modeling and verificationAMS
    5Bandgap reference IP – Analysis, modeling and verificationAMS
    6Voltage regulator IP – Analysis, modeling and verificationAMS
    7Internal oscillator IP – Analysis, modeling and verificationAMS
    8Power-on Reset IP – Analysis, modeling and verificationAMS
    9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
    10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
    11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
    12SoC integration – 3PIAS ProjekatDD+DV
    13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
    14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
    15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
    16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
    17VIP Development – PCI ExpressDV
    18VIP Development – DDRDV
    19VIP Development – EthernetDV
    20VIP Development – USBDV
    21VIP Development – CSIDV
    22VIP Development – DSIDV
    23VIP Development – UNIPRODV
    24VIP Development – I3CDV
    25VIP Development – SLIMbusDV
    26VIP Development – HDMIDV
    Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.