Open Positions

IC Layout Engineer

For our offices in Belgrade and Novi Sad, Serbia, we are looking for proactive and motivated Analog Custom IC Layout Engineers to join our dynamic team. You will be a part of analog layout team, constituted of engineers with different level of experience, from analog layout experts to juniors. Your daily work will be challenging and you will have the opportunity to cooperate with industry experts on the state-of-the-art processes, tools, and flows.

Analog electronics0%

Analog IC design/layout0%

CMOS and bipolar technology0%

CAD tools 0%

Senior Design Verification Engineer

As a Senior Design Verification Engineer, you will play a key leadership role within the digital IP/SoC design verification team, guiding engineers of varying experience levels, from junior team members to seasoned professionals. You will take ownership of complex verification activities, drive technical excellence, and mentor your team to ensure successful project execution. In this role, you will work closely with industry experts, leveraging cutting-edge processes, tools, and methodologies. Additionally, you will be responsible for tracking project progress, supporting team development, and serving as the primary technical point of contact for clients, ensuring continuous improvements and seamless communication.

Leadership0%

C/C++0%

SystemVerilog/UVM0%

SoC0%

Technical Expert - Design Verification

As a Technical Expert in Design Verification, you will focus on solving complex technical challenges in digital IP/SoC verification. Your main responsibilities will include developing advanced verification environments, debugging simulation issues, and optimizing verification strategies. With deep knowledge of processor architecture, Systems-on-Chip, and verification frameworks, you will ensure high technical standards in project execution. You will work closely with clients and teams to improve verification processes while staying hands-on with the latest tools and technologies.

Technical skill set0%

UVM0%

IP/SoC0%

Project Management0%

On the other hand, if a suitable position in relation to your level of expertise is not on the list but you still feel you belong with Elsys, feel free to send us your curriculum vitae and a cover letter.

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.