Tape out: The Chip is ready! IC Layout Internship Program

You’ll have the opportunity to work on multiple projects that will enhance your engineering capabilities, encourage creativity and out-of-the-box thinking.

Belgrade, June 23rd, 2022

 

Minimize the effects of technological process imperfections, provide the required circuit functionality, and fulfil the factory criteria, so that the integrated circuit can be manufactured. Sounds good? Let’s learn more about IC Layout engineering!

 

Milos Lazic, Analog IC Layout Engineer at Elsys Eastern Europe, will introduce you to IC Layout engineering and the way you can start your career in this area of expertise. Milos will emphasize the scale of impact and responsibilities IC Layout engineering has on the process of silicon chip development and what it takes to be successful.

 

“Elsys Eastern Europe has been successfully designing integrated circuit layouts for 15 years. During this period, the engineers had the opportunity to work on the development of several dozen integrated circuits in various technologies from robust to state-of-the-art such as 7 nanometer FinFET technologies.”

 

We’ve put huge effort in creating a such an internship program that will easily open a path towards becoming and IC Layout engineer. First of all, we must emphasise that IC Layout is a very challenging and an exciting career path. Because you’ll have the opportunity to work on multiple projects that will enhance your engineering capabilities, encourage creativity and out-of-the-box thinking.

 

You’re probably thinking how this position is going to inspire me to be more creative. Well, here’s a fun fact. Did you know that an IC Layout engineer can add his personal signature on every silicon chip he designed? With this said, the layout of analog circuits is designed with Full custom methodology where a layout engineer has absolute control over the positions of each component on the chip and each connection.

 

The internship program has three modules lasting three months in total. During this period, candidates go through theoretical lectures and practical exercises.”

 

When it comes to theoretical lecturing segment of the internships, our interns will have a chance to work with our best engineers who continuously try to facilitate the learning process and pass their knowledge to our interns. During the practical teaching segment, our interns can work on the most modern equipment and licensed software that are the standard in the development of integrated circuits. Practice is performed on the real analog circuits that are developed for the needs of commercial projects in our company.

 

If you’ve enjoyed reading this article, then look no further. Elsys Eastern Europe is the place for you.

Check out our open IC Layout internship and apply!

 

APPLY

 

WHERE PASSION LEADS TO EXCELLENCE

Related posts

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.