Tape out: The Chip is ready! IC Layout Internship Program

Milos will introduce you to IC Layout Engineering and how you can start your career in this area of expertise.

Belgrade, July 19th, 2023

 

Minimize the effects of technological process imperfections, provide the required circuit functionality, and fulfill the factory criteria to manufacture the integrated circuit. Sounds good? Let’s learn more about IC Layout engineering!

 

Milos Lazic, Analog IC Layout Engineer at Elsys Eastern Europe, will introduce you to IC Layout Engineering and how you can start your career in this area of expertise. Milos will emphasize the scale of impact and responsibilities IC Layout Engineering has in the process of silicon chip development and what it takes to be successful.

 

DID YOU KNOW?

Fun fact 1: The layout of analog circuits is designed with Full custom methodology where a layout engineer has absolute control over the positions of each component on the chip and each connection.

 

Fun fact 2: Did you know an IC Layout engineer can add his signature on every silicon chip he designed?

 

APPLY NOW 

 

WHERE PASSION LEADS TO EXCELLENCE

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2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.