Over 7 years of experience in mixed-signal domain allows us to successfully cope with any challenge that modern verification methodologies have to offer.

Our biggest advantage is that we are here from the beginning. When mixed-signal verification started to expand, we went through all its phases together with the world’s leading companies. Therefore, we can keep up with the latest AMS verification techniques without spending too much time getting acquainted.
This enabled us to create our own AMS verification flow which is in use whenever our clients lack the expertise in this domain.

VERIFICATION FIELDS

Working closely with many customers, our engineers are fully able to integrate into customer’s verification teams or take full ownership of a verification project. Our expertise covers:

  • Analog IP verification
  • Analog modeling (Verilog-AMS, wreal, EEnet)
    • SoC’s internal analog modules
    • External – test-bench analog modules (e.g. antenna)
    • Model “calibration” – functional test against the schematic
  • Full top-level verification in both UVM and direct methodologies
  • Power aware, GLS simulations
  • Stress testing, performance analysis
  • Fault injection
  • AMS simulation speed-up (by adapting models or analog simulator settings)

PROCESS

Scope of work covered by our teams:

  • Project management and planning
  • Verification tools setup
  • Functional spec assessment
  • Verification Metrics, verification plan and test plans definition
  • Verification environment architecture definition, development and maintenance
  • Test suite development and debug
  • Regression runs

INDUSTRIES

Products we have verified are being developed for different industries:

  • Automotive
  • Audio
  • Consumer Electronics / Multimedia
  • Health/Medical
  • Telecommunications

Contact us

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GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.