Mixed-Signal Verification Engineer
Key Responsibilities / Duties:
- Development of Verilog A/AMS models of AMS IP
- Analog and mixed-signal circuits analysis
- Development of AMS design verification environment
- Using Cadence toolchain for AMS verification
Qualification Requirements:
- You hold an engineering master or bachelor degree in an electronic or microelectronic field or equivalent by experience
- Familiar with basic analog circuitry, CMOS, and bipolar technology, VHDL or Verilog HDL language
- Cadence tools knowledge is a plus
- Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc)
- Familiarity with behavioral Verilog / Verilog-A code
- Motivated, proactive, and team player
- Good knowledge of English language
Benefits:
- Integration program in a professional, young & dynamic team
- Professional development opportunities
- Competitive salaries & benefits
- Compensation package includes also additional health insurance, sport & social activities
- International work environment
You can find out more about our benefits here.
