Technical Expert – Verification Engineer
Key Responsibilities / Duties:
- Define and implement advanced verification strategies for complex digital designs.
- Lead the development of verification environments from the ground up, ensuring efficiency, scalability and reusability.
- Development and implementation of verification plans and analysis of corresponding metrics.
- Act as the primary technical liaison with clients, ensuring alignment with project requirements.
- Manage project delivery, ensuring verification goals, quality, and timelines are met.
- Identify and drive technical improvements in verification methodologies and workflows.
- Support internal teams with cross-domain expertise and knowledge sharing.
Qualification & Requirements:
- 10+ years of experience in digital verification, with deep expertise in UVM/SystemVerilog or Specman/e.
- Proven track record in project management and successful verification implementations.
- Extensive experience in debugging Gate-level simulations (GLS) and handling complex verification scenarios.
- Strong knowledge of processor architecture, ASIC/FPGA/SoC architectures and various verification approaches.
- Expertise in C/C++, as well as scripting languages (Python, Perl, Tcl).
- Strong leadership skills with the ability to mentor teams and drive innovation.
- Highly motivated, detail-oriented, and an excellent problem solver.
- Proficiency in English for effective communication with teams and clients.
Benefits:
- Key technical leadership role with influence over verification strategies.
- Competitive compensation and benefits package, including health insurance and social activities.
- Opportunities for career growth and collaboration with top-tier industry experts.
- High-impact role in cutting-edge digital design verification projects.
You can find out more about our benefits here.