Pick a team.
Face a challenge.
Surprise yourself.
You already picked
the right profession.
We have prepared two challenges for you: game-design and image processing, both on FPGA-based platform. The game design challenge is assembled for students without any experience in HDL languages, while image processing is reserved for students already familiar with HDL (VHDL/Verilog).
Assemble your team with your fellow colleagues from one of the three Universities:
This is the first hardware design competition in Serbia, organized by Elsys Eastern Europe together with ETF in Belgrade.
Game Design
Your application should contain a list of your three team members, their bio (age, year of study, department) and the team name. You can also apply solo – and we will pick the team for you prior the competition.
Applying solo or as a team with a short motivational letter is mandatory, because we would like to know what is your drive, and your passion in the world of electronics.
Depending on your level of experience in HDL, competition organizer will select the most relevant challenge for your team and assign either the game design or the image processing challenge. By doing so, we want to ensure that all of you feel comfortable yet challenged in accordance with your current knowledge.
The main prize is Samsung Galaxy Watch 5 for each member of the winning team in both categories. One prize is not enough for all the talent we expect to see on this competition.
Elsys Eastern Europe has prepared internship offers for the best-in-show.
The competition will take place in Elsys Eastern Europe, Airport City, Belgrade
Transportation and accommodation will be provided for free for all competitors located outside the Belgrade.
We have prepared two challenges for you: game-design and image processing, both on FPGA-based platform. The game design challenge is assembled for students without any experience in HDL languages, while image processing is reserved for students already familiar with HDL (VHDL/Verilog).
Assemble your team with your fellow colleagues from one of the three Universities:
This is the first hardware design competition in Serbia, organized by Elsys Eastern Europe together with ETF in Belgrade.
Your application should contain a list of your three team members, their bio (age, year of study, department) and the team name. You can also apply solo – and we will pick the team for you prior the competition.
Applying solo or as a team with a short motivational letter is mandatory, because we would like to know what is your drive, and your passion in the world of electronics.
Depending on your level of experience in HDL, competition organizer will select the most relevant challenge for your team and assign either the game design or the image processing challenge. By doing so, we want to ensure that all of you feel comfortable yet challenged in accordance with your current knowledge.
The main prize is Samsung Galaxy Watch 5 for each member of the winning team in both categories. One prize is not enough for all the talent we expect to see on this competition. Elsys Eastern Europe has prepared internship offers for the best-in-show.
The competition will take place in Belgrade, Elsys Eastern Europe, Airport City, Belgrade
Transportation and accommodation will be provided for free for all competitors located outside the Belgrade.
# | Topic | Domain |
1 | Clock domain crossing – issues and how to overcome them | DD |
2 | Scheduling techniques and their implementation for queue servicing | DD |
3 | Functional safety approaches implementation in digital design | DD |
4 | Temperature sensor IP – Analysis, modeling and verification | AMS |
5 | Bandgap reference IP – Analysis, modeling and verification | AMS |
6 | Voltage regulator IP – Analysis, modeling and verification | AMS |
7 | Internal oscillator IP – Analysis, modeling and verification | AMS |
8 | Power-on Reset IP – Analysis, modeling and verification | AMS |
9 | IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDP | DV |
10 | IP verification – MAC merge sublayer IP – MMSL – MAC Rx | DV |
11 | IP verification – MAC merge sublayer IP – MMSL – MAC Tx | DV |
12 | SoC integration – 3PIAS Projekat | DD+DV |
13 | SoC integration – ARM – Cortex M0 platform Integration using ARM SDK | DD+DV |
14 | SoC integration – ARM – Cortex M3 platform Integration using ARM SDK | DD+DV |
15 | SoC Verification – interdisciplinary themes – SW coverage collection and analysis | DV |
16 | SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture) | DV |
17 | VIP Development – PCI Express | DV |
18 | VIP Development – DDR | DV |
19 | VIP Development – Ethernet | DV |
20 | VIP Development – USB | DV |
21 | VIP Development – CSI | DV |
22 | VIP Development – DSI | DV |
23 | VIP Development – UNIPRO | DV |
24 | VIP Development – I3C | DV |
25 | VIP Development – SLIMbus | DV |
26 | VIP Development – HDMI | DV |