Pick a team.
Face a challenge.
Surprise yourself.

You already picked
the right profession.

We have prepared two challenges for you: game-design and image processing, both on FPGA-based platform. The game design challenge is assembled for students without any experience in HDL languages, while image processing is reserved for students already familiar with HDL (VHDL/Verilog).

Can you bring the project
to its completion in limited time?

Assemble your team with your fellow colleagues from one of the three Universities:

This is the first hardware design competition in Serbia, organized by Elsys Eastern Europe together with ETF in Belgrade.

Don’t just accept the challenge – challenge yourself!

Game Design

Image Processing &
Hardware Accelerator

* HDL mandatory

competition specs

Your application should contain a list of your three team members, their bio (age, year of study, department) and the team name. You can also apply solo – and we will pick the team for you prior the competition.

Applying solo or as a team with a short motivational letter is mandatory, because we would like to know what is your drive, and your passion in the world of electronics.

Depending on your level of experience in HDL, competition organizer will select the most relevant challenge for your team and assign either the game design or the image processing challenge. By doing so, we want to ensure that all of you feel comfortable yet challenged in accordance with your current knowledge.

application specs

prizes

The main prize is Samsung Galaxy Watch 5 for each member of the winning team in both categories. One prize is not enough for all the talent we expect to see on this competition.
Elsys Eastern Europe has prepared internship offers for the best-in-show.

The competition will take place in Elsys Eastern Europe, Airport City, Belgrade

Transportation and accommodation will be provided for free for all competitors located outside the Belgrade.

Pick a team.
Face a challenge.
Surprise yourself.

You already picked
the right profession.

We have prepared two challenges for you: game-design and image processing, both on FPGA-based platform. The game design challenge is assembled for students without any experience in HDL languages, while image processing is reserved for students already familiar with HDL (VHDL/Verilog).

Can you bring the project
to its completion in limited time?

Assemble your team with your fellow colleagues from one of the three Universities:

This is the first hardware design competition in Serbia, organized by Elsys Eastern Europe together with ETF in Belgrade.

Don’t just accept the challenge
– challenge yourself!
competition specs
Game Design
Image processing & Hardware accelerator
* HDL mandatory

Your application should contain a list of your three team members, their bio (age, year of study, department) and the team name. You can also apply solo – and we will pick the team for you prior the competition.

 

Applying solo or as a team with a short motivational letter is mandatory, because we would like to know what is your drive, and your passion in the world of electronics.

 

Depending on your level of experience in HDL, competition organizer will select the most relevant challenge for your team and assign either the game design or the image processing challenge. By doing so, we want to ensure that all of you feel comfortable yet challenged in accordance with your current knowledge.

application specs

Apply now!

prizes

The main prize is Samsung Galaxy Watch 5 for each member of the winning team in both categories. One prize is not enough for all the talent we expect to see on this competition. Elsys Eastern Europe has prepared internship offers for the best-in-show.

The competition will take place in Belgrade, Elsys Eastern Europe, Airport City, Belgrade

Transportation and accommodation will be provided for free for all competitors located outside the Belgrade.

GRADUATION THESIS LIST

#TopicDomain
1Clock domain crossing – issues and how to overcome themDD
2Scheduling techniques and their implementation for queue servicingDD
3Functional safety approaches implementation  in digital designDD
4Temperature sensor IP – Analysis, modeling and verificationAMS
5Bandgap reference IP – Analysis, modeling and verificationAMS
6Voltage regulator IP – Analysis, modeling and verificationAMS
7Internal oscillator IP – Analysis, modeling and verificationAMS
8Power-on Reset IP – Analysis, modeling and verificationAMS
9IP verification – MAC merge sublayer IP – MMSL – Link Layer Discovery Protocol control – LLDPDV
10IP verification – MAC merge sublayer IP – MMSL – MAC RxDV
11IP verification – MAC merge sublayer IP – MMSL – MAC TxDV
12SoC integration – 3PIAS ProjekatDD+DV
13SoC integration – ARM – Cortex M0 platform Integration using ARM SDKDD+DV
14SoC integration – ARM – Cortex M3 platform Integration using ARM SDKDD+DV
15SoC Verification – interdisciplinary themes – SW coverage collection and analysisDV
16SoC Verification – interdisciplinary themes – CPU instructions provided by SV TB instead of reading from Memory; (SV + ARM architecture)DV
17VIP Development – PCI ExpressDV
18VIP Development – DDRDV
19VIP Development – EthernetDV
20VIP Development – USBDV
21VIP Development – CSIDV
22VIP Development – DSIDV
23VIP Development – UNIPRODV
24VIP Development – I3CDV
25VIP Development – SLIMbusDV
26VIP Development – HDMIDV
Please note, although thesis are created in collaboration with professors, you need to get final approval by your UNI professor.